RISC-V

Addressing Next-Generation Compute Requirements

Unleashing the power of data through RISC-V initiatives

The open source model, proven by the success of Linux®, now has a hardware platform in RISC-V to enable the next generation of innovation. Another reason is that the configurability RISC-V provides is unparalleled. By leveraging the open collaboration and flexibility of RISC-V, Western Digital can create processors that are purpose-built for data-centric applications.

RISC-V is an open ISA enabling a new era of processor innovation.

The RISC-V SweRV Core Family

Performance leading embedded RISC-V cores

Western Digital has developed four RISC-V cores, the 64 bit, multicore SweRV Core EHX3 and three 32 bit cores, the SweRV Core EH1, EH2 and EL2.

The SweRV Cores will be used in a variety of Western Digital products in the near future. The 32 bit cores have been open sourced in CHIPS Alliance github.

CHIPS Alliance is an organization that develops open source hardware and open source software design tools. It is a barrier free, collaborative environment which lowers the cost of RTL development.

SweRV Core EHX3

SweRV Core EHX3 is a 64 bit, multi core capable, 9 stage pipeline core.

SweRV Core EHX3 Architecture

SweRV Core EHX3 multi core implementation with Tilelink.

SweRV Core EH1

The Western Digital SweRV Core EH1 is a 32-bit, 2-way superscalar, 9 stage pipeline core.

SweRV Core EH2

The SweRV Core EH2 was built off of the EH1, but adds dual threaded capability for additional performance.

SweRV Core EL2

The SweRV Core EL2 is a smaller core with moderate performance. It was designed to replace state machines and other logic functions in SoCs.

Core Name	RISC-V Type	Pipeline Stages	Threads	Size @ TSMC	CoreMarks/Mhz
SweRV CPU EHX3	RV64GBC	9- dual issue	Single	-	6
SweRV Core EH1	RV32IMC	9- dual issue	Single	.11mm @ 28nm	5.7
SweRV Core EH2	RV32IMAC	9- dual issue	Single	-	6
SweRV Core EH2	RV32IMAC	9- dual issue	Dual	.067 @ 16nm	7.8
SweRV Core EL2	RV32IMC	4- single issue	Single	.023 @ 16nm	4.3

Report

Market Trends: Custom ICs Based on RISC-V Will Enable Cost-Effective IoT Product Differentiation¹

Gartner’s Report on RISC-V momentum in IoT and business environments

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Technical Brief

RISC-V and Open Source Hardware Address New Compute Requirements

Download a summary of the RISC-V initiatives Western Digital has invested in.

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Article

The Journey of RISC-V Implementation²

A historical look at the progress and future of RISC-V

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Report: The Linley Group Microprocessor Report

WD Rolls Its Own RISC-V Core³

Western Digital Opens Superscalar SweRV CPU Source to others.

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Industry Article

How Data-Centric Applications Can Capitalize on RISC-V Processor Innovation⁴

RISC-V is more than a processor ISA. The open nature of the specification enables new compute architectures such as OmniXtend.

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Software Infrastructure

Western Digital Firmware Infrastructure (Abstraction Layer Firmware)

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Events

The RISC-V Foundation regularly conducts events and workshops. Participate in an event near you.

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Featured Videos

Video

Strategic Innovation: RISC-V at Western Digital

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Video

RISC-V 2020 Summit: The March of RISC-V

Western Digital 2020 RISC-V Summit Keynote discussing next generation storage and compute. Siva Sivaram discusses Western Digital’s first RISC-V SweRV Core SoC in a prototype SSD. Updates to the SweRV Core family and an invitation to collaborate on a unified memory standard for heterogeneous processing.

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Video

RISC-V SweRV Core Family Overview

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Video

RISC-V Summit 2019: SweRV Cores Roadmap

Technical details on Western Digital’s new RISC-V SweRV Core EH2 and EL2.

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Video

RISC-V Summit 2020: The Open Source Hardware Roadmap - Zvonimir Bandic, Chairman, CHIPS Alliance

The RISC-V open ISA has enabled a new generation of processing architectures. There now exists an open hardware group, CHIPS Alliance where organizations, non-profits, individuals, and academia can collaborate to solve the next generation of processing challenges. See the milestones that CHIPS Alliance has already accomplished and learn about our roadmap and future vision for open source hardware.

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Video

RISC-V Summit 2019: RISC-V and Chips Alliance Address new Compute Requirements

CHIPS Alliance keynote at the 2019 RISC-V Summit explaining the organization and the latest development efforts.

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Video

How to set up OmniXtend coherent memory fabric demo with RISC-V and Tofino

A detailed video explaining how to set up an OmniXtend demo. This demo uses two FPGA boards and a programmable Ethernet switch. It explains the programming of the FPGA boards and the P4 code needed to run on the switch.

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Video

RISC-V Summit 2020: Omnixtend Boot Protocol and Coherent Scaleout - Dejan Vucinic, Western Digital Corporation

OmniXtend has become the de facto standard for building multi-socket RISC-V systems. Recent efforts within the Interconnects Workgroup in CHIPS Alliance resulted in the definition of an initialization and configuration protocol which enables the construction of massively parallel systems of arbitrary size.

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Video

RISC-V Summit 2019: An Open and Coherent Memory Centric Architecture Enabled by RISC-V

Technical update on OmniXtend, a cache coherent Ethernet based memory fabric.

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Video

RISC-V Summit 2020: Where Is the 32-Bit Glibc Port? - Alistair Francis, Western Digital

This talk will cover the Y2038 Unix Epoch overflow problem and what is being done to fix it. It will describe how and why this applies to the 32-bit RISC-V glibc port.

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Video

RISC-V Summit 2019: Headline Sponsor Western Digital presents GCC Compiler Code Size Density

The latest GCC code density improvements for RISC-V.

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Video

RISC-V Summit 2019: Headline Sponsor Western Digital presents RISC V Hypervisor Support

Technical update on QEMU and hypervisor support for RISC-V.

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Forward Looking Statements
This webpage may contain forward-looking statements, including, but not limited to, statements regarding our product and technology portfolio, the capacities, capabilities and applications of, and market for, our products, our strategies and growth opportunities, and market trends. These forward-looking statements are subject to risks and uncertainties that could cause actual results to differ materially from those expressed in or implied by the forward-looking statements. The risks and uncertainties are discussed more fully in Western Digital Corporation’s filings with the Securities and Exchange Commission, including our most recently filed periodic report, to which your attention is directed. Readers are cautioned not to place undue reliance on these forward-looking statements and we undertake no obligation to update these forward-looking statements to reflect subsequent events or circumstances, except as required by law.

Disclosures
1. Source: Market Trends: Custom ICs Based on RISC-V Will Enable Cost-Effective IoT Product Differentiation by Amy Teng (Gartner, 6/5/2020)
2. Source: The Journey of RISC-V Implementation by Ted Marena (AllAboutCircuits.com, 9/10/2019)
3. Source: WD Rolls its own RISC-V Core (Microprocessor report, 2/4/2019).
4. Source: How Data-Centric Applications Can Capitalize on RISC-V Processor Innovation by Ted Marena (AllAboutCircuits.com, 3/20/2019).
5. Source: CHIP Alliance’s Newly Enhanced SweRV Cores Available to All for Free (CHIP Alliance, 5/14/2020)

RISC-V

Unleashing the power of data through RISC-V initiatives

RISC-V is an open ISA enabling a new era of processor innovation.